The present invention relates to digital circuits and, more particularly to digital circuits employed in memory devices in which data is transferred between two independent clock domains with a predetermined timing relationship.
Memory devices are constantly evolving in the directions of faster speed and higher memory density. To this end, dynamic random access memory (DRAM) devices have evolved from simple DRAM devices to EDO to SRAM to DDR SDRAM to SLDRAM, the latter of which is the subject of much current industry interest. SLDRAM has a high sustainable bandwidth, low latency, low power, user upgradability and support for large hierarchical memory applications. It also provides multiple independent banks, fast read/write bus turn-around, and the capability for small fully pipelined bursts.
One characteristic of SLDRAM is that it is a double data rate device which uses both the positive- and negative-going edges of a clock cycle to READ and WRITE data to the memory cells and to receive command and FLAG data from a memory controller.
An overview of SLDRAM devices can be found in the specification entitled xe2x80x9cSLDRAM Architectural and Functional Overview,xe2x80x9d by Gillingham, 1997 SLDRAM Consortium (Aug. 29, 1997), the disclosure of which is incorporated by reference herein.
Because of the required high speed operation of SLDRAM, and other contemporary memory devices, system timing is a very important aspect of the operation of such devices. The SLDRAM often uses an external system clock signal CCLK to capture commands and an internally generated master clock signal MCLK to perform other operations, such as data transfers. Existing SLDRAM circuits utilize delay circuits and tapped digital delay locked loop (DLL) circuits to generate required output data clocks as well as the master clock signal MCLK. Typically, the internal master clock is generated by the DLL from the external CCLK using a model of the memory device output path so that the timing, as seen by output pads of the device, is stable despite temperature and voltage variations.
While the output timing remains stable, the internal timing varies as a function of the output model. The timing of the master clock changes (i.e., experiences increased delays) by as much as 1.3 nsecs from the slow to the fast operating/process corner. The capture circuitry of the memory device typically contains delay and latching circuitry to center the external capture clock CCLK in the center of a data eye of incoming data. The delay and latching circuitry, however, also varies with temperature and voltage variations, but in a direction opposite to that of the master clock signal from the DLL. The overall clock delay variation is 1 nsec (i.e., decreased delay) from the slow to the fast operating/process corner. The net effect, however, is that the capture clock timing and master clock timing varies by 2.3 nsecs from corner to corner. The variation makes crossing the clock domains, from capture clock to master clock, very difficult since the variation is almost a full clock cycle at 800 Mb/sec (i.e., 400 MHz).
The capture latching circuitry of the memory device is designed to maintain the validity of the data bits for a full clock cycle (i.e., one rising edge and one falling edge of the clock). For a double data rate device, there is a latch for rising edge data and another latch for falling edge data. Each latch is designed to hold its respective latched data valid for one clock cycle. The period in which the data is valid is often referred to as the data eye or data envelope. For a 400 MHz system, for example, a full clock cycle (i.e., two ticks) would be approximately 2.5 nsecs.
The captured data is transferred within the master clock domain in accordance with an edge of the master clock signal MCLK (rising edge for rising edge data and falling edge for falling edge data). The placement of the master clock signal MCLK edge within the captured data envelope is optimized by selecting the DLL tap that fed the master clock signal MCLK. Unfortunately, as the operating corner is swept from a slow corner to a fast corner, the master clock signal MCLK edge that registered a given data bit moves outside of the data envelope and an earlier master clock signal MCLK edge moves inside the envelope.
Changing the master clock signal MCLK edges at the clock domain boundary changes the latency of the device, since the command essentially enters the device two ticks earlier (in relation to the master clock). The relationship between the master clock MCLK and capture clock CCLK signals is typically unknown and variable. Causes for the unknown/variable relationship between the master clock MCLK and capture clock CCLK signals include temperature and voltage variations of the device. In addition, the frequency of the device, which defines the period of the clock cycles for the master clock MCLK and capture clock CCLK signals, affects the range of phase variation between the master clock MCLK and the capture clock CCLK. This range of phase relationship is fixed for the chosen frequency of operation for the device.
These variations are compensated for by other circuitry (i.e., output model and DLL) with the intentions that each captured command bit has a data eye or data envelope that should be centered about a master clock signal MCLK edge when transferred to the master clock domain. Currently, the latching circuitry of the conventional memory device keeps the information valid only during one clock cycle (a clock cycle is two clock ticks and has a range often referred to as xe2x80x9c2xcfx80 radiansxe2x80x9d). Due to a potential xc2x12xcfx80 radians variation between the master clock MCLK and capture clock CCLK signals and another xc2x12xcfx80 radians uncertainty between the signals, however, the captured data may be clocked into the master clock domain on the wrong MCLK edge.
Accordingly, there is a need and desire to keep the master clock edge within the capture data envelope over the entire operating range despite temperature and voltage variations that may effect the timing of the memory device. It is also desirable to establish a relationship between the master clock and capture clock signal and to maintain the relationship to keep the master clock edge within the capture data envelope over the entire operating range despite variations that may effect the timing of the memory device.
The present invention provides a memory device that keeps a master clock edge within the capture data envelope over the entire operating range of the device despite temperature and voltage variations that may effect the timing of the memory device.
The above and other features and advantages are provided by a method and apparatus that expands the data envelope of captured data to a predetermined number of clocks cycles. The predetermined number of clock cycles is large enough to ensure that an internally generated master clock edge remains within the data envelope over the entire operating range of the memory device. This way, captured data remains valid and can be properly transferred to the master clock domain from a capture clock domain despite temperature and voltage variations that may effect the timing of the memory device.